The invention relates generally to techniques for improving the conversion accuracy of chopper-stabilized delta-sigma modulators, particularly chopper-stabilized delta-sigma modulators of the type shown in commonly owned U.S. Pat. No. 6,201,835, and more particularly to reducing chopping residue noise and associated gain drift and offset drift inaccuracies.
The closest prior art is believed to include the above-mentioned U.S. Pat. No. 6,201,835 which is entitled “Frequency-shaped pseudo-random chopper stabilization circuit and method for delta-sigma Modulator” issued to Binan Wang on Mar. 13, 2001, and incorporated herein by reference.
Prior Art FIG. 1A herein is a replication of FIG. 1 of above-mentioned U.S. Pat. No. 6,201,835 (the '835 patent), which shows a system for reducing sensitivity of an integrated circuit chopper-stabilized amplifier to intermodulation. Block 29 in Prior Art FIG. 1A shows a chopper-stabilized delta-sigma modulator which is identical to or substantially the same as in subsequently described FIG. 2. The output of chopper-stabilized delta-sigma modulator 29 is connected to the input of a decimation filter 38. One or more integrators, such as integrators 36 and 37, of chopper-stabilized delta-sigma modulator 29 are clocked by a frequency-shaping pseudo-random chopper clock generator circuit 1.
However, the prior art chopper-stabilized delta-sigma modulator 29 has the shortcoming that the disclosed pseudorandom chopper clock generator 1 produces a low frequency “chopping residue” signal. The fixed frequency chopping signal applied to chopper-stabilized delta sigma modulator 29 results in converting an internal offset voltage (which is due to mismatching of circuit components) into the low fixed frequency “chopping residue” signal, which is a low frequency AC signal. The magnitude of the chopping residue signal is a function of the magnitude of the above-mentioned offset voltage. The '835 patent teaches that intermodulation causes “idle tone” signals to be generated in the delta sigma modulator output signal when fixed frequency chopping signals are used. The '835 patent teaches that such idle tones, which are aliased back to the base band, can be avoided by providing the chopping signal at random frequencies. The '835 patent also discloses “frequency shaping” of the pseudorandom chopping signal. The low-frequency shaping results in the advantage of reducing the spread of low-frequency energy in the band of interest so as to improve overall noise performance.
The frequency-shaped pseudorandom chopping disclosed in the '835 patent provides a “first order” improvement in the amount of noise in the delta sigma modulator 29. However, the “first order” frequency-shaping is not sufficient to adequately suppress the chopping residue signal for applications in which very low noise is needed.
Referring to subsequently described FIG. 6, the upper curve labeled “A” shows the chopping residue noise for the prior art delta-sigma modulator 29 shown in FIG. 1A with the frequency-shaped curve shown in FIG. 1B (which is a replication of FIG. 3C of the '835 patent). Chopping residue noise curve “A” in FIG. 6 has a “noisy” shape, with a low-frequency noise level that is a function of the offset voltage, and has a level of roughly −150 dB, which is too high for some applications.
Another disadvantage of using the frequency-shaped pseudorandom sequence generator of the '835 patent to generate chopping clock signals for chopper stabilization of amplifier circuitry and delta-sigma modulators is that because of the finite length of the pseudorandom sequence it “wraps around” and starts over, causing noise spikes each time the sequence starts over. For example, if the pseudo-random sequence generator is 10 bits in length, it will produce the same sequence and wrap around every 210 clock cycles, thereby producing a low frequency periodic noise spike.
The closest prior art also is believed to include U.S. Pat. No. 6,411,242 entitled “Oversampling Analog-to-Digital Converter with Improved DC Offset Performance” issued to Oprescu et al. Jun. 25, 2002. This reference utilizes a fixed chopping frequency equal to one half of the data output frequency to allow switching the polarity of the analog input signal and output signal every chopping cycle. The offset error is removed from the output signal in the digital domain, but that approach reduces the digital data output rate by a factor of two because the analog-to-digital converter must perform two conversions before it can effectively average the output data so as to cancel the offset error.
Thus, there is an unmet need for an improved technique for reducing the noise of a chopper-stabilized oversampling analog-to-digital converter using frequency-shaped pseudo-random chopping clock signals.
There also is an unmet need for an improved technique for reducing conversion errors in a chopper-stabilized delta-sigma analog-to-digital converter using frequency-shaped pseudorandom chopping clock signals.
There also is an unmet need for a chopper-stabilized amplifier circuit in a chopper-stabilized delta-sigma modulator which has the benefits of the very low idle tone magnitudes achieved by the circuitry of commonly owned U.S. Pat. No. 6,201,835 and which also has the benefits of very low chopping residue noise.
There also is an unmet need for an improved technique for reducing conversion errors in a chopper-stabilized delta-sigma analog-to-digital converter using frequency-shaped pseudorandom chopping clock signals and also for reducing low frequency periodic noise spikes resulting from wrap-around operation of a pseudorandom sequence generator used to produce the chopping clock signals.
There also is an unmet need for an improved technique for reducing conversion errors in a chopper-stabilized delta-sigma analog-to-digital converter using frequency-shaped pseudorandom chopping clock signals and also for improving the speed of conversion over the prior art.